The present invention relates generally to integrated circuit design, and, more particularly, to static random access memory (SRAM) with improved read/write stability.
SRAM is a type of memory device that stores data in an array of cells that do not need to be constantly refreshed as long as it remains being supplied with power. FIG. 1 schematically illustrates a conventional 6-T SRAM cell 100 comprised of pull-up devices 102 and 104, pull-down devices 106 and 108, and pass gate devices 110 and 112. The pull-up device 102 is a PMOS transistor having a source coupled to a supply voltage VDD, and a drain coupled to a drain of the pull-down device 106, which is an NMOS device having its source coupled to ground or VSS, which can be any voltage lower than the supply voltage VDD. The pull-up device 104 is also a PMOS transistor having a source coupled to the supply voltage VDD, and a drain coupled to a drain of the pull-down device 108, which is an NMOS device having its source coupled to the source of the pull-down device 106, and to ground or VSS. The gates of the pull-up device 102 and the pull-down device 106 are coupled together with the drains of the pull-up device 104 and 108 at a node 114. Likewise, the gates of the pull-up device 104 and the pull-down device 108 are coupled together with the drains of the pull-up device 102 and the pull-down 106 at a node 116. The pass gate device 110 connects the node 116 to a bit line BL, whereas the pass gate device 112 connects the node 114 to a complementary bit line BLB.
The pull-up device 102 and the pull-down device 106 make up an inverter cross-coupled with another inverter comprised of the pull-device device 104 and the pull-down device 108. When the pass gate devices 110 and 112 are turned off, the nodes 114 and 116 latch a value and its complement therein. In read or write operation, the signal on the word line WL is asserted to turn on the pass gate device 110 and 112 to enable the nodes 114 and 116 to be access through the bit line BL and the complementary bit line BLB.
One drawback of the conventional SRAM cell 100 is that the data stored in the cell may be disturbed during read or write operation. In a physical SRAM chip, a plurality of cells is arranged in an array where a row of cells are connected by a single word line. In read/write operation, the signal on a word line is asserted to turn on the pass gate devices of a row of cells. Although only one cell on the selected row is desired for the read/write operation, the pass gate devices of other cells on the selected row are also turned on, thereby causing the data stored in those cells to be in direct connection with their corresponding bit lines and complementary bit lines. As a result, the data stored in those cells can be disturbed by the voltages on the bit lines and the complementary bit lines.
In order to address the read/write disturbance issue, an 8-T SRAM cell 200 has been proposed as shown in FIG. 2. The conventional 8-T SRAM cell 200 comprised of pull-up devices 202 and 204, pull-down devices 206 and 208, pass gate devices 210 and 212, a read select device 218, a read control device 220. The pull-up device 202 is a PMOS transistor having a source coupled to a supply voltage VDD, and a drain coupled to a drain of the pull-down device 206, which is an NMOS device having its source coupled to ground or VSS. The pull-up device 204 is also a PMOS transistor having a source coupled to the supply voltage VDD, and a drain coupled to a drain of the pull-down device 208, which is an NMOS device having its source coupled to the source of the pull-down device 206, and to ground or VSS. The gates of the pull-up device 202 and the pull-down device 206 are coupled together with the drains of the pull-up device 204 and the pull-down device 208 at a node 214. Likewise, the gates of the pull-up device 204 and the pull-down device 208 are coupled together with the drains of the pull-up device 202 and the pull-down device 206 at a node 216. The pass gate device 210 connects the node 216 to a bit line BL, whereas the pass gate device 212 connects the node 214 to a complementary bit line BLB.
The read select device 218 and the read control device 220 are serially connected along a read bit line RBL. The gate of the read select device 218 is controlled by the read word line RWL, whereas the gate of the read control device 220 is connected to the node 214 at the drains of the pull-up device 204 and the pull-down device 208.
In read operation, the signal on the RWL is asserted to turn on the read select device 218. The value at the node 214 determines whether or not the read control device 220 is turned on. For example, if the value at the node 214 is a logic “1,” the read control device 220 is turned on, such that a signal can be read through the read bit line RBL, whereas if the value at the node 214 is a logic “0,” the read control device 220 is turned off, such that a signal cannot be read through the read bit line RBL. Because the read bit line RBL is not directly connected to the node 214, the charges stored at node 214 are not disturbed during the read operation.
Although the SRAM cell 200 is proposed to address the read disturbance issue of the conventional 6-T cells, it does not eliminate the read disturbance completely for the whole cell array. In a physical SRAM chip, a plurality of cells are arranged in an array where a row of cells are connected by a single read word line and write word line, respectively. In a read operation, the signal on a read word line RWL is asserted to turn on the read select transistor 218, and the data stored in SRAM cells could be read out without any read disturbance. In a write operation, the gate of the write select transistors 210 and 212 are both connected to a write word line WWL. Although only one cell on the selected row is desired for the write operation, the pass gate devices of other not-to-be written cells on the selected row are also turned on and enter dummy read mode, thereby causing the data stored in those cells to be in direct connection with their corresponding bit lines and complementary bit lines. As a result, the data stored in those unselected cells can still be disturbed by the voltages on their corresponding bit lines and the complementary bit lines. Apparently, the aforementioned RWL and WWL may be merged into the same word line for a compact layout with compromised performance.
Thus, what is needed is an SRAM design that eliminates data disturbance during read/write operation.